Typically integrated circuits (ICs) are manufactured through the manipulation of photographic masks. Today, custom logic can be built on an IC that contains an array of transistors with programmable interconnections. These are referred to as gate arrays. The logic of the transistors and the interconnect are configurable based on the user's needs. The architecture of these gate arrays consists of rows (columns) of transistors separated by a distance that is used to connect the rows (columns) together. The space between the rows is also used to bring connections to the I/O logic which is usually around the periphery of the IC.
A fully customizable IC consists of many layers. A typical gate array has some number of base layers required to build the transistors, with the top four layers of the IC being programmable. The four programmable layers are used to define the logic function of the array of transistors as well as provide the interconnect between the defined logic functions.
FIG. 1 shows a device, usually a transistor, fabricated as p-channel metal-oxide semiconductor (PMOS) transistor 100. The fabrication of PMOS transistor 100 involves a series of steps. Referring to FIG. 1, PMOS transistor 100 consists of substrate 101 which is doped with n.sup.+. The n.sup.+ doping indicates a heavily doped substrate. Diffused into substrate 101 are two p.sup.+ regions 102 and 103. These are typically implanted using ion-beam technology. Once again, the p.sup.+ designation indicates a strong doping of p carriers. An oxide layer 105 is created on top of the n.sup.+ region 101 between p.sup.+ regions 102 and 103. A polysilicon (Si) layer 104 is built on the oxide layer 105. An insulation layer 109 is grown over substrate 101. The polysilicon layer 104 and p.sup.+ regions 102 and 103 represent the three parts of a transistor device.
To create the transistor device, PMOS transistor 100, p.sup.+ regions 102 and 103 and polysilicon 104 are connected. The connection to the device occurs using contacts (i.e., holes) 106, 107, and 108. These contacts are connected to a first metalization layer 110. First metalization layer 110 could be aluminum. An insulation layer, oxide 111, is fabricated over metalization layer 110. Holes, known as vias, are created in insulation layer 111. The vias are formed using well-known mask technology, wherein a photographic process, in conjunction with an etchant, creates a hole. Next, a second metalization layer 113, is placed over insulation layer 111. In fabricating metalization layer 113, metal flows into the vias and connects to metalization layer 110. Vias are shown as 112a, 112b and 112c in FIG. 1. Finally, an insulation layer, oxide 114, covers the entire wafer, including PMOS transistor 100, to complete the fabrication process. NMOS transistors are built similarly but with opposite dopings.
As described above with respect to FIG. 1, logic units are formed by coupling multiple transistors together. Each logic unit can perform a different logic function. Thus, custom logic can be built by connecting individual logic functions together. In gate arrays, rows of same sized transistors are created and equally spaced apart. To customize the logic, sets of transistors are then connected together to form a logic unit and the logic units are connected through the spacing, i.e. channel, between the rows of transistors (which are now formed into logic units). Usually, a minimum set of transistors, possibly two PMOS and two NMOS, is required to create a logic function. This minimum set is known as a base cell. A logic unit may consist of one or more base cells.
To create the logic units, known as personalizing the transistors or base cells, and the connections, a place and route software chooses the location of the logic units and how they are to be connected. To electrically create and connect the logic units, the wafer is processed using the four steps referenced above (contact, first metalization, via, second metalization). This entire process is known as "personalizing the gate array." To complete these steps, four separate masking steps are required, one for each processing step. The personalization and connection of the units is performed using both metalizations and their corresponding interconnections. A common routing technique would utilize the first metalization for portions of the path which run vertically between the rows, i.e. in the channel space, and use the second metalization for the portions of the path that run horizontally through the channel space. The first and second metalizations are coupled with vias. This allows a path to avoid collisions with other paths since all horizontal runs are insulated from vertical runs.
The problem with the prior art is that four stages of fabrication are required to create custom logic. Each stage requires four separate masks and a considerable amount of time. Furthermore, if a problem occurs in the fabrication of any of the stages, the entire process must be repeated.
The present invention avoids these problems of customizing integrated circuits by utilizing gate arrays which are fabricated up to the last metal layer (i.e., the second metalization layer) and personalizing and connecting base cells to form logic units in the array at the second metalization layer using portions of the first metalization layer. This allows for a faster turn-around time for creating the custom chip and better reliability.